The development of integrated circuits, in particular for microprocessors, systems on a chip, digital signal processors (DSP) and similar highly integrated devices, leads to increasingly complex designs with an increasing number of semi-conductor devices arranged on smaller and smaller surfaces. Such integrated devices are usually optimized to fulfil predefined timing requirements. However, in particular in the context of mobile devices becoming more and more ubiquitous and the drive for more efficient and cheaper use of energy in large computing centres, it has become desirable to increase the power efficiency of designs of integrated circuits. Due to the complex nature of such circuits, it is often difficult to identify structures which potentially might be power optimized.